The present invention relates, in general, to high voltage protection circuitry and, more particularly, to Electrostatic Discharge (ESD) protection circuitry.
It is well known that monolithic integrated circuits may become damaged by exposing their input or output terminals to large and sudden voltage transients such as electrostatic discharges. For example, electrostatic charge may build up on personnel and test equipment. When the charged person or piece of test equipment contacts the input or output terminals of the integrated circuit, the built-up electrostatic charge discharges and may force large currents into the integrated devices. The large currents may rupture dielectric materials within the integrated devices such as gate oxides or they may melt conductive materials such as polysilicon or aluminum interconnects, thereby irreparably damaging the integrated circuits.
Generally, integrated circuit manufacturers include protection devices that shunt current away from input and output circuitry within integrated devices to prevent the integrated devices from being damaged by large voltage transients. One technique for protecting integrated device input and output circuitry is to form current shunting structures from parasitic elements present in the integrated devices. A disadvantage of this technique is that the breakdown voltage of these structures is limited by the processing techniques for manufacturing the integrated circuit. Another technique for protecting these circuits is to improve the energy dissipation capability of the protection circuitry. This is done by laying out the protection circuit to have larger geometries, wider metal interconnects, more and larger contacts, etc. A disadvantage of this approach is it increases the size of the integrated device and thus decreases the number of integrated circuits per semiconductor wafer, thereby increasing the cost of manufacturing the integrated circuits.
Accordingly, it would be advantageous to have an integrated device for protecting an integrated circuit from large voltage transients and a method of manufacturing the integrated device. It would be of further advantage for the integrated device to occupy a small area and be capable of protecting integrated circuit input and output structures.